Semiconductor device

ABSTRACT

A semiconductor integrated circuit includes non-volatile memory elements (PM 1 , PM 2 ), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM 1 , DM 2 ), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to flow a channel current according to the threshold voltage of the non-volatile memory element.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor integrated circuit (semiconductor device) including electrically erasable and programmable non-volatile memory elements and, more particularly, to a technology effectively applied to, for example, a microcomputer or a memory LSI in which non-volatile memory elements, which are capable of being mounted without adding a new process to an existing CMOS process and formed by applying a single layer poly flash technology, are applied to a fault recovery and the like.

[0002] A single layer poly flash technology constituting the memory cell of a non-volatile memory by a single layer poly silicon gate is disclosed in Japanese Patent Laid-Open No. 334190/1994 (which corresponds to U.S. Pat. No. 5,465,231), U.S. Pat. No. 5,440,159, U.S. Pat. No. 5,504,706, Japanese Patent Laid-Open No. 212471/1992 (which corresponds to U.S. Pat. Nos. 5,457,335, 5,767,544 and 6,064,606), and “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid State Circuits, VOL. 29, NO. 3, March 1994, pp. 311-316. For example, in a non-volatile memory cell by a single layer poly flash technology disclosed in Japanese Patent Laid-Open No. 334190/1994, a first conductivity type MOS transistor is formed on a semiconductor substrate and a plate electrode is formed in a second conductivity type well via an insulating layer, wherein the gate electrode of the MOS transistor and plate electrode are connected to each other and function as a floating gate and wherein the second conductivity type well functions as a control gate.

[0003] In Japanese Patent Laid-Open No. 212471/1992, there is also disclosed a technology for utilizing an electrically programmable non-volatile memory (EPROM) as a recovery circuit of a read on memory (ROM). Further, it is described in the patent gazette that a non-volatile memory element having a first layer gate structure in accordance with the present invention can be also used as an electrically programmable and erasable non-volatile memory element, in which a write operation is performed by hot carriers and an erase operation is performed by a tunnel current produced by applying a high voltage to a source or a drain, or the write and erase operations are performed by the tunnel current.

[0004] On the other hand, a technology for differentially utilizing two non-volatile memory elements from the viewpoint of preventing a malfunction is disclosed in Japanese Patent Laid-Open No. 163797/1992, Japanese Patent Laid-Open No. 263999/1989, Japanese Patent Laid-Open No. 74392/1992, Japanese Patent Laid-Open No. 127478/1990, Japanese Patent Laid-Open No. 129091/1992, Japanese Patent Laid-Open No. 268180/1994, and U.S. Pat. No. 5,029,131. In a differential type memory cell structure, one non-volatile memory element is set in a writing state and the other non-volatile memory element is set in an erasing state and signals read out in parallel from both the non-volatile memory elements are differentially amplified and the logic value of memory information is judged according to which output of the non-volatile memory elements in the writing state or in the erasing state becomes either an input to an inversion side or a non-inversion side.

SUMMARY OF THE INVENTION

[0005] The present inventor has studied a differential type non-volatile memory cell structure and found the following points. That is, the present inventor has found that, even in the differential type non-volatile memory cell structure, there is presented a problem that the rate of occurrence of faulty reading caused by degradation in a charge holding characteristic is largely affected by a threshold voltage at the initial state where a floating gate has no charge, a threshold voltage in a writing state or in an erasing state, and the state of a word line electric potential when a read operation is performed. Here, FIG. 49 and FIG. 50 which will be hereinafter described are not the drawings showing publicly known technologies, but the drawings made by the present inventor for the purpose of facilitating the understanding of the present invention.

[0006] In FIG. 49, there is illustrated the threshold voltage distribution of a memory cell in the case where an initial threshold voltage (Vthi) is set at a relatively high value. For example, the initial threshold voltage (Vthi) is set at a value higher than the mean value of a low threshold voltage (VthL) in an erasing state and a high threshold voltage (VthH) in a writing state. The initial threshold voltage (Vthi) is a threshold voltage in a state of thermal equilibrium. A read word line electric potential (Vread) is set in the middle region between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In this setting state, the voltage difference between the high threshold voltage (VthH) and the initial threshold voltage (Vthi) is small, that is, the amount of accumulated charges is small and a self-electric field intensity applied to a gate oxide film is also small. As a result, a decrease in the threshold voltage caused by the leak of charges from the floating gate, that is, data retention resists occurring. On the other hand, an electric field in the direction in which electrons are injected into the floating gate is applied to the tunnel oxide film of the memory cell at the low threshold voltage (VthL) by the word line voltage when the read operation is performed to also generate weak hot electrons near a drain to thereby generate a charge gain, which increases the threshold voltage. Since this undesirable increase limit of the threshold voltage reaches the initial threshold voltage (Vthi), when the threshold voltage is higher than the read word electric potential (Vread), the data is inversed and can not be read out. Therefore, the fact that the characteristic shown in FIG. 49 is comparatively strong for the data retention but is weak for the charge gain has been made clear by the present inventor.

[0007] In contrast to this, in FIG. 50, there is illustrated the threshold voltage distribution of the memory cell in the case where the initial threshold voltage (Vthi) is set at a relatively low value. For example, the initial threshold voltage (Vthi) is set at a value lower than the mean value of the low threshold voltage (VthL) and the high threshold voltage (VthH). The read word line electric potential (Vread) is set in the middle region between the high threshold voltage (VthH) and the initial threshold voltage (Vthi). In this setting state, the voltage difference between the low threshold voltage (VthL) and the initial threshold voltage (Vthi) is small and hence the charge gain caused by the word line voltage when the read operation is performed resists occurring. On the other hand, since a memory cell having the high threshold voltage (VthH) has the large voltage difference with respect to the initial threshold voltage (Vthi), it has a large amount of accumulated charges and high self-electric field intensity applied to the gate oxide film. As a result, an undesirable decrease in the threshold voltage easily arises from the leak of charges from the floating gate. Since this undesirable decrease limit of the threshold voltage reaches the initial threshold voltage (Vthi) and when the threshold voltage is lower than the read word line electric potential (Vread), the data is inversed and can not be read out. The fact that since the characteristic shown in FIG. 50 is comparatively strong for the charge gain and the difference between the low threshold voltage (VthL) and the read word line electric potential (Vread) is large, it can produce a comparatively large read current but is weak for the data retention has been found by the present inventor.

[0008] In this manner, the high threshold voltage (VthH) of the non-volatile memory element is caused to gradually approach the initial threshold voltage (Vthi) in the state of thermal equilibrium by the leak of charges (data retention) by the self-electric field applied to the gate oxide film, and the low threshold voltage (VthL) is caused to gradually approach the initial threshold voltage (Vthi) in the state of thermal equilibrium by the electric field in the direction of the charge gain by the word line voltage (Vread) when the read operation is performed, or by the drain current. It has been recognized by the present inventor that it is difficult to keep the high reliability of continuous reading for a long time more than 10 years because of the degradation in characteristics of both the data retention and the charge gain, even if the differential type memory cell structure is employed.

[0009] One object of the present invention is to provide a semiconductor integrated circuit capable of improving a long-term data holding performance by memory cells employing non-volatile memory elements.

[0010] Another object of the present invention is to provide a semiconductor integrated circuit mounted with non-volatile memories capable of remarkably reducing the rate of occurrence of faulty reading without adding any absolutely new process to an ordinary logic circuit process, a general-purpose DR process, or the like.

[0011] Still another object of the present invention is to provide a technology utilizing a flash memory cell constituted by a single layer polysilicon gate as a recovery circuit of a memory module or a memory circuit formed in the a semiconductor device.

[0012] The above-mentioned and other objects and new features of the present invention will be clear from the description of the present specification and the accompanying drawings.

[0013] The general outlines of the typical inventions disclosed in this application will be described as follows.

[0014] The present invention employs a memory cell structure which can eliminate the need for flowing a channel current through a non-volatile memory element in a read operation and the need for applying a large word line voltage to thereby prevent a date inversion caused by a charge gain and the like.

[0015] (1) A semiconductor integrated circuit in accordance with the present invention has a non-volatile memory element including a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode, and capable of having different threshold voltages; and a read transistor element including a second source electrode, a second drain electrode and the floating gate electrode as a gate electrode, and capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element, as a basic constitution which a memory cell or an information memory cell has. A signal generated according to the mutual conductance of the read transistor element is transmitted to transmission means.

[0016] The function of the read transistor element is not limited to the above first aspect in accordance with the present invention, but it can be also grasped by the second aspect that the read transistor element includes a second source electrode, a second drain electrode and the above-mentioned floating gate electrode as a gate electrode, and is capable of having different switching states according to the threshold voltage which the non-volatile memory element has, or by the third aspect that the read transistor element includes a second source electrode, a second drain electrode and the above-mentioned floating gate electrode as a gate electrode, and is capable of having different threshold voltages according to the threshold voltage which the non-volatile memory element has.

[0017] In the above description, assume that, for example, when one threshold voltage of the non-volatile memory cell is a relatively high threshold voltage (threshold voltage in a writing state where electrons are injected into the floating gate) and the other threshold voltage is a low threshold voltage (threshold voltage in an erasing state where electrons are emitted from the floating gate), the transistor element is cut off in the state of the high threshold voltage and is on in the state of the low threshold voltage (naturally, the transistor element may be in a reverse state depending on the conductivity type of the transistor element). The erasing state of the non-volatile memory cell can be accomplished, for example, by disposing the first drain electrode and the control gate electrode of the non-volatile memory element at 0 volt like the ground voltage of a circuit and the first source electrode of the non-volatile memory element at 6 volts and by ejecting electrons from the floating gate electrode to the first source electrode by a tunnel current. The writing state can be accomplished, for example, by disposing the first drain electrode and the control gate electrode of the non-volatile memory element at 5 volts and the first source electrode of the non-volatile memory element at 0 volt like the ground voltage of the circuit and by injecting hot electrons generated in the first drain electrode into the floating gate electrode.

[0018] Since the floating gate electrode of the non-volatile memory element is the gate electrode of the above-mentioned read transistor element, the read transistor element is set in a switching state or a mutual conductance according to the electron injection state or the electron ejection state, in other words, the writing state or the erasing state of the floating gate electrode. Therefore, even if a select level is not applied to the control gate electrode, a current according to the switching state or the mutual conductance can be flown to the transmission means (transmission circuit). A circuit diagram based on this example is shown in FIG. 1. In this circuit, a select level is not applied to the control gate electrode and hence it is recommended that a depression type MIS transistor be employed as the above-mentioned read transistor element in a sense of ensuring an amount of signal necessary for the transmission means.

[0019] On the other hand, when an enhancement type MIS transistor is employed as the above-mentioned read transistor element, it is desirable in a sense of ensuring an amount of signal necessary for the transmission means that a select level be applied to the control gate electrode also in the read operation. A circuit form based on this example is shown in a memory section in FIG. 44. It should be understood that in this form, the read transistor element has different threshold voltages according to the electron injection state or the electron ejection state, in other words, the writing state or the erasing state of the floating gate electrode.

[0020] As described above, in the read operation, it is not necessary to flow a channel current according to the threshold voltage of the non-volatile memory element. Accordingly, in the read operation, the source electrode and the drain electrode of the non-volatile memory element may be disposed at 0 volt like the ground potential of the circuit. Therefore, weak hot electrons are not injected into the floating gate electrode from the first drain electrode. Here, if the control gate electrode is also disposed at the ground potential of the circuit, a tunnel current is not generated, either. Granting that a select level is applied to the control gate electrode, the tunnel current is not generated between the first drain electrode and the floating gate electrode. Although a weak tunnel current or the like might be generated between the second drain electrode of the read transistor element and the floating gate electrode, if the select level of the control gate electrode is low, it can be concluded that any problem is not substantially presented. Alternatively, in the case where a drain voltage is applied to the read transistor element via MIS transistors vertically staked as shown in FIG. 44, the drain voltage itself is lowered and hence it can be concluded that any problem is not substantially presented.

[0021] In this manner, a problem of data inversion caused by the charge gain is not presented in the read operation. This can improve a data holding performance and reduce the rate of faulty reading.

[0022] (2) A constitution may be adopted that the non-volatile memory element includes a capacitor element having a capacitor electrode on a first semiconductor region functioning as a control gate electrode via an insulating layer and a MIS transistor including a source electrode, a drain electrode and a gate electrode which are formed on a second semiconductor region, wherein the capacitor electrode is connected to the gate electrode and functions as a floating gate electrode.

[0023] From another aspect of the present invention, the non-volatile memory element may be composed of: a first conductivity type first well region formed on a semiconductor substrate; a second conductivity type second well region formed on the semiconductor substrate; a second conductivity type first source electrode region which is formed on the first well region and is to be connected to a first signal line; a second conductivity type first drain electrode region which is formed on the first well region and is to be connected to a second signal line; a first insulating film formed on the principal surface of the first well region at the position between the first source electrode region and the first drain electrode region; a second insulating film formed on the principal surface of the second well region; a floating gate electrode region formed on the first and second insulating films; and a control gate electrode region which is formed on the second well region and is to be connected to a third signal line.

[0024] In any case, a semiconductor integrated circuit including the non-volatile memory elements can be fabricated without adding any absolutely new process to an ordinary logic circuit process or a general-purpose DRAM process such as a CMOS process, a single layer polysilicon gate process, or the like.

[0025] (3) In order to reduce the rate of faulty reading by further taking data retention measures to an information memory cell to which measures have been taken against the charge gain by adopting a structure in which the non-volatile memory elements are paired with the read transistor elements, it is recommended to adopt the following constitution.

[0026] First, a pair of non-volatile memory elements described above and a pair of read transistor elements described above are provided, and the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and the pair of read transistor elements are connected in series to the transmission means. In this constitution, both of the pair of non-volatile memory elements are programmed in the writing state or in the erasing state. When the pair of non-volatile memory elements are in the writing state, the pair of read transistor elements are off. Here, although the possibility that held charges will be made to leak from the non-volatile memory elements in the writing state by some reason is not zero in a probability, even if the held charges leak from one non-volatile memory element, the series path of the read transistors is held cut off and hence the probability that the held charges will leak from both of the pair of non-volatile memory elements is extremely low. This makes it possible to improve the data retention measures and to further reduce the rate of faulty reading.

[0027] As a circuit form based on this constitution, there is provided the one shown in FIG. 1 in which depression type MIS transistors are vertically stacked as the read transistor elements or the circuit shown in the memory cell section in FIG. 44 in which enhancement type MIS transistors are arranged in series as the read transistor elements.

[0028] Second, a pair of non-volatile memory elements described above and a pair of read transistor elements described above are provided, and the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and the pair of read transistor elements are connected in parallel to the transmission means. Also in this constitution, in a manner similar to the above example, both of the pair of non-volatile memory elements are programmed into the writing state or into the erasing state. Since this second example assume that the conductivity type of the read transistor element is different from that of the above example, when the non-volatile memory elements are in the writing state, both of the pair of read transistor elements are on. Here, although the possibility that held charges will leak from the non-volatile memory elements in the writing state by some cause is not zero in a probability, even if the held charges leak from one non-volatile memory element, the parallel path of the read transistor elements is held on and hence the probability that the held charges will leak from both of the pair of non-volatile memory elements is extremely low. This makes it possible to improve the data retention measures and to further reduce the rate of faulty reading.

[0029] (4) As a use of the non-volatile memory elements and the read transistor elements, it is thought that redundancy in their structures can be used for recovering faults of the semiconductor integrated circuit. Here, the semiconductor integrated circuit has a plurality of unit information cells, each of which is composed of the pair of non-volatile memory elements and the pair of read transistor elements, and an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, wherein the plurality of unit information cells are made the memory circuit of recovery information to a circuit to be recovered. This can improve the reliability of a fault recovery.

[0030] A fuse program circuit for memorizing recovery information according to the melting state of a fuse element may be provided as another recovery information memory circuit to the circuit to be recovered. It is possible to improve the rate of recovery, in other words, the yield of the semiconductor integrated circuit, by recovering faults detected in the step of a wafer by means of a fuse program circuit and by using the above-mentioned electric program circuit for the faults detected after a burn-in test. It is not possible to recover the faults after the burn-in test only by the fuse program circuit. Only the use of the electric program circuit increases the scale of the circuit or the area of the chip as compared with the case where the fuse program circuit is also used with the electric circuit.

[0031] The circuit to be recovered may be the memory array in which a DRAM is built. Further, the circuit to be recovered may be the memory array of a DRAM in which a microcomputer is built. Still further, the circuit to be recovered may be the memory array of an SRAM in which a microcomputer is built.

[0032] (5) In order to ultimately reduce the rate of faulty reading, it is recommended that a semiconductor integrated circuit be constituted by a plurality of unit information cells each of which is composed of the pair of non-volatile memory cells and the pair of read transistor elements, wherein a part of the plurality of unit information cells are made a region for holding an error correction code to the memory information of the remaining unit information cells, an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, and an ECC circuit capable of correcting an error to the read information of the plurality of unit information cells.

[0033] In order to ensure an error correction function by the ECC circuit, it is recommended that the electric program circuit has an operation mode of prohibiting writing into the unit information cell, when an ECC circuit is effective.

BRIEF DESCRIPTION OF THE DRAWING

[0034]FIG. 1 is an equivalent circuit diagram to illustrate one example of a memory cell as an information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0035]FIG. 2 is a voltage-current characteristic plot of a read MIS transistor shown in FIG. 1.

[0036]FIG. 3 is a cross-sectional view illustrating a device structure to realize a circuit configuration shown in FIG. 1.

[0037]FIG. 4 is the cross-sectional view taken on a line A-A′ in FIG. 3.

[0038]FIG. 5 is the cross-sectional view taken on a line B-B′ in FIG. 3.

[0039]FIG. 6 is the plane layout of FIG. 3.

[0040]FIG. 7 is an illustration to show the state of voltage applied to each terminal when writing, erasing, or reading is performed in the circuit shown in FIG. 1.

[0041]FIG. 8 is an equivalent circuit diagram to illustrate the second example of a memory cell as an information memory cell included by a semiconductor integrated circuit device in accordance with the present invention.

[0042]FIG. 9 is the plane layout of the memory cell shown in FIG. 8.

[0043]FIG. 10 is an illustration to show the state of voltage applied to each terminal when writing, erasing, or reading is performed to the memory cell shown in FIG. 8.

[0044]FIG. 11 is a circuit diagram to illustrate a mat selection recovery circuit diagram of a DRAM which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0045]FIG. 12 is a circuit diagram to illustrate a mat selection recovery circuit when a conventional laser-melted fuse is used.

[0046]FIG. 13 is a block diagram schematically illustrating a circuit block of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0047]FIG. 14 is a plan view of a chip of a system LSI which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0048]FIG. 15 is a flow chart to show a testing flow of a system LSI in accordance with the present invention.

[0049]FIG. 16 is a plan view of a chip of a 1-G bit DRAM which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0050]FIG. 17 is a flow chart to show a testing flow of the DRAM shown in FIG. 16.

[0051]FIG. 18 is a first cross-sectional structural view to illustrate a manufacturing process of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0052]FIG. 19 is a second cross-sectional structural view to illustrate a manufacturing process of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0053]FIG. 20 is a third cross-sectional structural view to illustrate a manufacturing process of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0054]FIG. 21 is a fourth cross-sectional structural view to illustrate a manufacturing process of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention.

[0055]FIG. 22 is an equivalent circuit diagram illustrating a highly reliable flash memory cell which is another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0056]FIG. 23 is an equivalent circuit diagram illustrating a small area flash memory cell which is further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0057]FIG. 24 is an equivalent circuit diagram illustrating a voltage sense type flash memory cell which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0058]FIG. 25 is a plane layout illustrating a metal cover type flash memory cell which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0059]FIG. 26 is the cross-sectional view taken on a line C-C′ in FIG. 25.

[0060]FIG. 27 is a plane layout illustrating a metal cover type flash memory cell which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0061]FIG. 28 is the cross-sectional view taken on a line D-D′ in FIG. 27.

[0062]FIG. 29 is an equivalent circuit diagram illustrating a flash memory cell employing a p-channel type MIS transistor which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0063]FIG. 30 is a voltage-current characteristic plot relating to read MIS transistors EM1, EM2.

[0064]FIG. 31 is a plane layout view of the memory cell in FIG. 29.

[0065]FIG. 32 is an equivalent circuit diagram illustrating a 2 NAND type flash memory cell which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0066]FIG. 33 is a voltage-current characteristic plot of a MIS transistor used for the 2 NAND type flash memory in FIG. 32.

[0067]FIG. 34 is a plane layout view of the memory cell in FIG. 32.

[0068]FIG. 35 is a circuit diagram illustrating a self-learning type 2 NAND gate which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0069]FIG. 36 is a signal transmission characteristic plot to an input signal of the circuit in FIG. 35.

[0070]FIG. 37 is a plane layout view of the memory cell in FIG. 35.

[0071]FIG. 38 is a circuit diagram of a circuit for monitoring the degradation of the gate oxide film to which a non-volatile information memory element in accordance with the present invention is applied.

[0072]FIG. 39 is an equivalent circuit diagram illustrating a differential amplification type flash memory cell which is still further another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention.

[0073]FIG. 40 is a plane layout view of the flash cell in FIG. 39.

[0074]FIG. 41 is a block diagram of a fuse module which is still another example of an integrated circuit in accordance with the present invention.

[0075]FIG. 42 is a circuit diagram illustrating an example circuit of a non-volatile memory block.

[0076]FIG. 43 is an illustration exemplifying the control embodiment of a unit information cell by a bias controller.

[0077]FIG. 44 is a circuit diagram illustrating one example of a unit information cell.

[0078]FIG. 45 is a read timing chart in the state where a fuse module is practically used after a program to a unit information cell is completed.

[0079]FIG. 46 is a plan view to illustrate a layout pattern of a memory cell section.

[0080]FIG. 47 is a timing chart of a program operation to a unit information cell according to the control embodiment in FIG. 43.

[0081]FIG. 48 is a logic circuit diagram illustrating one example of logic for generating a Hamming code by means of a Hamming generator.

[0082]FIG. 49 is an illustration exemplifying the threshold voltage distribution of the non-volatile memory cell in the case where an initial threshold voltage (Vthi) is set at a relatively high value.

[0083]FIG. 50 is an illustration exemplifying the threshold voltage distribution of the non-volatile memory cell in the case where an initial threshold voltage (Vthi) is set at a relatively low value.

[0084]FIG. 51 is a voltage-current characteristic plot of a read MIS transistor constituted by a non-volatile enhancement type memory cell.

[0085]FIG. 52 is a block diagram to illustrate, in the connection of circuits, a relationship between a laser fuse and an electric fuse.

[0086]FIG. 53 is a longitudinal cross-sectional view illustrating one example of a dynamic memory cell in a DRAM.

[0087]FIG. 54 is a circuit diagram exemplifying the non-volatile memory cell in FIG. 1 in detail.

DETAILED DESCRIPTION OF THE INVENTION Source Line Sharing Type Memory Cell Structure

[0088] In FIG. 1, there is shown an equivalent circuit illustrating one example of a memory cell as an information memory cell included by a semiconductor integrated circuit in accordance with the present invention. In FIG. 7, there is exemplified the state of voltage applied to each terminal when a write operation, an erase operation, or a read operation is performed in the circuit shown in FIG. 1.

[0089] In the circuit shown in FIG. 1, the floating gates Vf of a plurality of non-volatile memory elements PM1, PM2 are used as the gate electrodes of a plurality of read MIS transistors DM1, DM2 which are OR-logically connected to each other and the word line PWL of the non-volatile memory elements PM1, PM2 is used as the grounding potential of the circuit.

[0090] That is, according to FIG. 1, the floating gates Vf of two non-volatile memory elements PM1, PM2 are used as the gate electrodes of n-channel type read MIS transistors DM1, DM2 which are connected in series to each other, respectively. For the sake of convenience, the junctions where the non-volatile memory elements PM1, PM2 are connected to a read data line are referred to as drain electrodes, and the junctions where the non-volatile memory elements PM1, PM2 are connected to a source line Vss are referred to as source electrodes. The source electrodes of the non-volatile memory elements PM1, PM2 and the source electrodes of the read MIS transistors DM1, DM2 share the source line Vss together.

[0091] In FIG. 54, there is illustrated in detail the non-volatile memory elements PM1, PM2. The respective non-volatile memory elements PM1, PM2 have MIS capacitor elements MP1 b, MP2 b, each of which has a capacitor electrode on a first semiconductor region functioning as a control gate electrode via an insulating layer, and MIS transistors PM1 a, PM2 a, each of which has a first source electrode, a first drain electrode and a gate electrode which are formed in a second semiconductor region. In short, each of the MIS capacity elements MP1 b, MP2 b is constituted by a MIS transistor capacitor in which the source electrode, the drain electrode, and the back gate are commonly connected to each other. Each of the capacitor electrodes of the MIS capacitor elements MP1 b, MP2 b is commonly connected to each of the gate electrodes of the MIS transistors PM1 a, PM2 a to function as the floating gate electrode Vf.

[0092] When a write operation is performed to the above-mentioned non-volatile memory elements PM1, PM2, as shown in FIG. 7, a write data line PDL is disposed at a voltage of 5V, a write word line PWL is disposed at a voltage of 5V, and a read data line RDL, a read word line RWL and a source line Vss are disposed respectively at a voltage of 0V. This injects the hot electrons generated at the drain electrode into the floating gate electrode to increase the threshold voltages of the non-volatile memory elements PM1, PM2.

[0093] When an erase operation is performed to the above-mentioned non-volatile memory elements PM1, PM2, as shown in FIG. 7, the write data line PDL, the write word line PWL, the read data line RDL, and the read word line RWL are disposed respectively at a voltage of 0V, and the source line Vss is disposed at a voltage of 6V. This makes a tunnel current remove electrons from the floating gate into the source electrode to decrease the threshold voltages of the non-volatile memory elements PM1, PM2.

[0094] The above-mentioned read MIS transistors DM1, DM2 are different in the switching state or the mutual conductance between the writing state and the erasing state of the non-volatile memory elements PM1, PM2. When the read operation is performed to the non-volatile memory elements PM1, PM2, as shown in FIG. 7, the read data line RDL and the read word line RWL are disposed at a voltage of 1.8V and the signal lines PDL, PWL, and Vss are disposed respectively at 0V. An n-channel type select MIS transistor SM receiving the read word line on the gate electrode enables the above-mentioned read MIS transistor DM1 to connect to the read data line RDL. The read data line RDL is brought into conduction with he source line Vss when both the read MIS transistors DM1, DM2 are in the ON state.

[0095] In this manner, when the read operation is performed, the write data line PDL, the write word line PWL, and the source line Vss are fixed at the ground potential (0V) of the circuit, respectively. Accordingly, at this time, weak hot electrons are not injected into the floating gate or electrons are not injected thereinto by the tunnel current.

[0096] In FIG. 2, there is illustrated the voltage-current characteristics of the above-mentioned read MIS transistors DM1, DM2. The initial threshold voltage (Vthndm) of the read MIS transistors DM1, DM2 is set in the range of voltage which is higher than the electric potential of the floating gate electrode Vf (approximately −2V) when the write operation is performed to the non-volatile memory elements PM1, PM2 to inject charges thereinto (in the writing state) and is lower than the electric potential of the floating gate electrode Vf (approximately −0V) in the initial state of the erasing state where the write operation is not performed to the non-volatile memory elements PM1, PM2. In other words, the read MIS transistors DM1, DM2 are depression type transistors. Into the semiconductor regions of the read MIS transistors DM1, DM2 is introduced, for example, a low concentration of phosphorus.

[0097] In the writing state where charges are held in the floating gate, two read MIS transistors DM1, DM2 connected in series to each other are cut off and hence, even if the charges held by one element of the non-volatile memory elements PM1, PM2 leak by some cause to return the one element to the initial state, a current path via the read select MIS transistor SM is held cut off, which does not produce faulty reading.

[0098] As a precondition, the rate of faulty reading of a memory cell of 2-cell 1-bit type constituting 1 bit by 2 non-volatile memory elements PM1, PM2 will be calculated. For example, assuming that the probability of occurrence of faulty reading in 10 years in a memory cell of 1-cell 1-bit type constituting 1 bit by 1 non-volatile memory element is f, the probability Pa that both of two cells will be good is given by

Pa=(1−f)²  (1)

[0099] and the probability Pb that either of the two cells will be faulty is given by

Pb=(1−f)f+f(1−f)=2f(1−f)  (2)

[0100] and the probability Pc that both of the two cells will be faulty is given by

Pc=f²  (3)

[0101] where Pa+Pb+Pc=(1−f)²+2f(1−f)+f²=1

[0102] Letting the number of total bits of a chip be N, because a good cell means that it has no bit in the state of equation (3), N bits should be in the state of equation (1) or (2) and hence the probability Y of a good cell is given by

Y=Σ_(N) Ck Pa^(K) Pb^(N-K)  (4)

[0103] and the probability F of a faulty chip is given by

F=1−Y=1−Σ_(N) Ck Pa ^(K) Pb ^(N-K)  (5)

[0104] According to the binomial theorem,

Y=Σ _(N) Ck Pa ^(K) Pb ^(N-K)=(Pa+Pb)^(N)

={(1−f)²+2f(1−f)}^(N)

=(1−f ²)^(N)

[0105] Therefore, the equation (5) is reduced to

F=1−(1−f ²)^(N)  (6)

[0106] Here, since a memory cell of 1-cell 1-bit type is faulty even if one bit is faulty, the probability Y′ of a good memory cell of 1-cell 1-bit type is given by

Y=(1−f)^(N)  (7)

[0107] and the probability F′ of a faulty chip of 1-cell 1-bit type is given by

F′=1−(1−f)^(N)  (8)

[0108] Therefore, the rate of improvement R in the rate of a faulty chip by a semiconductor integrated circuit device in accordance with the present invention is given by

R=F/F′=1−(1−f ²)^(N)/{1−(1−f)^(N)}  (9)

[0109] When f<<1, the R is reduced to

R=F/F′≈f  (10)

[0110] Therefore, a remarkable improvement in the rate of a faulty chip can be accomplished.

[0111] According to the memory information cell structure shown in FIG. 1, the floating gate electrode of the non-volatile memory element becomes the gate electrode of the above-mentioned read transistor element and hence the read transistor element has the electron injection state or electron emission state of the floating gate electrode, in other words, a switching state or a mutual conductance state according to the writing state or the erasing state. Accordingly, even if a select level is not applied to the control gate electrode, a current according to the switching state or the mutual conductance state can be applied to the above transmission means. Since the select level is not applied to the control gate electrode, to ensure an amount of signal required of the transmission means, a depression type MIS transistor is employed as the above-mentioned read transistor element.

[0112] In the read operation, it is not necessary to apply a channel current according to the threshold voltage of the non-volatile memory element. Therefore, in the read operation, the source electrode and the drain electrode of the non-volatile memory element may be disposed at the ground potential of the circuit such as 0 volt, respectively. Therefore, the injection of weak hot electrons into the floating gate electrode from the first drain electrode is not generated. At this time, when the control gate electrode is disposed at the ground potential of the circuit, a tunnel current is not generated, either.

[0113] In this manner, in the reading operation, a problem of data inversion caused by the charge gain is not presented and hence it is possible to improve a performance of holding data for a long time and to realize a reduction in the rate of faulty reading.

[0114] Also, both of the read transistor elements are in the OFF state when both of the non-volatile memory elements are in the writing state. Although the possibility that the held charges will leak from the non-volatile memory elements in the writing state by some cause is not zero in a probability, even if the held charges leak from one non-volatile memory element, the series path of the above-mentioned read transistor elements is held cut off and hence the probability that the held charges will leak from both of the non-volatile memory elements is extremely low. This results in further providing complete data retention measures to the information memory cell to which charge gain measures have been taken by pairing the above-mentioned non-volatile memory elements with the above-mentioned read transistor elements and in further reducing the rate of faulty reading.

[0115] In FIG. 3, there is illustrated a device structure for realizing the circuit constitution shown in FIG. 1. The circuit structure shown in FIG. 1 is the one in which the above-mentioned non-volatile memory element capable of being fabricated by a manufacturing process such as a single layer polysilicon process or the like has a MIS transistor and a control gate with an insulating film interposed between itself and the floating gate of the MIS transistor, the control gate being formed of a layer doped with impurities.

[0116] Further describing the device structure in detail, as shown in the plane layout in FIG. 3, the control gate constituting the non-volatile memory element is formed of a second conductivity type semiconductor region 1 formed in a first conductivity type semiconductor region 2. The write MIS transistor constituting the non-volatile memory elements PM1, PM2 is formed in the active region 3 of the first conductivity type semiconductor region 2. The above-mentioned floating gate is formed of a conductive layer 7 which is arranged on the channel of the write MIS transistor and on the channel of the read MIS transistor formed in the active region 5 of the first conductivity type semiconductor region 2 via a gate insulating film. The above-mentioned control gate is formed of the second conductivity type semiconductor region 1 arranged under the active region 4 extended from the above-mentioned floating gate 7 via the gate insulating film.

[0117] In order to adjust the initial threshold voltages of the read MIS transistors DM1, DM2, a mask pattern 6 for introducing a second conductivity type impurity is added and a read word line 8 composed of the same conductive layer as the floating gate is formed. A reference numeral 9 designates a contact hole pattern, 10 designates a first metal wiring layer pattern, 11 designates a second metal wiring layer pattern, and 12 designates a third metal wiring layer pattern. A write word line PWL connected to the control gate of the non-volatile memory elements and a source line Vss, to which the source regions of the write MIS transistor and the read MIS transistor are connected, are formed of the first metal wiring layer, and a write data line PDL is formed of the second metal wiring layer, and a read data line RDL is formed of the third metal wiring layer.

[0118]FIG. 4 shows the cross section taken on a line A-A′ in FIG. 3, and FIG. 5 shows the cross section taken on a line B-B′ in FIG. 3. On the surface region of a first conductivity type semiconductor substrate 21 are formed a second conductivity type semiconductor region 22, functioning as the control gate of the non-volatile memory element, and a first conductivity type semiconductor region 23. In the first conductivity type semiconductor region 23, there are formed a write MIS transistor region of the non-volatile memory element isolated by an element isolating region 24 and provided with a gate insulating film 26, and a read MIS transistor region isolated by the element isolating region 24 and provided with the gate insulating film 26 and a second conductivity type impurity layer 25 for adjusting an initial threshold voltage. On the tops of the above second conductivity type semiconductor region 22, the write MIS transistor region, and the read MIS transistor region, there is arranged a floating gate 27 via the gate insulating film 26, and on the surface region of the second conductivity type semiconductor region 22 are formed a second conductivity type diffusion layer 31 and a first conductivity type diffusion layer 32. On the surface regions of the floating gate 27, the second conductivity type diffusion layer 31 and the first conductivity type diffusion layer 32, there is formed a metal silicide layer 29. On the peripheral portion of the floating gate 27, there is provided an insulating film side spacer 30, and a first interlayer insulating film 33, a first metal wiring layer 34, a second interlayer insulating film 35, a second metal wiring layer 36, a third interlayer insulating film 37, and a third metal wiring layer 38 are provided.

[0119]FIG. 6 is a plane layout in FIG. 3, and shows the layout of 4 bits constituting a memory cell array.

Source Line Separation Type Memory Cell Structure

[0120] In FIG. 8, a second example of a memory cell as an information memory cell including a semiconductor integrated circuit in accordance with the present invention is illustrated in an equivalent circuit.

[0121] The memory cell illustrated in the drawing is different from the one illustrated in FIG. 1 in that the source line Vs of the non-volatile memory elements PM1, PM2 is separated from the source line Vss of the read MIS transistor DM2.

[0122] In FIG. 9, there is illustrated the plane layout of the memory cell shown in FIG. 8. In FIG. 10, there are illustrated the states of voltages applied to the respective terminals when the write, erase and read operations are performed to the memory cell in FIG. 8.

[0123] Since the source line Vs of the non-volatile memory elements PM1, PM2 is independent, the voltage of 6V applied when the erase operation is performed is not applied to the read MIS transistors DM1, DM2. This can prevent the gate oxide films of the transistors from being degraded by voltage stress.

DRAM Mat Recovery Fuse

[0124] In FIG. 11, there is shown a DRAM mat selection recovery circuit diagram which is one example of a semiconductor integrated circuit in accordance with the present invention. Also, in FIG. 12, there is shown a mat selection recovery circuit diagram using a conventional laser-melted fuse. In order to replace the conventional laser-melted fuse with the non-volatile memory elements in accordance with the present invention, a column decoder 300 for controlling the write operation, a write driver 301, a row decoder 302, and a word driver 303 are added, and the write operation can realize the state equivalent to the state where a laser fuse is melted down and the read operation is performed as in the case with the conventional laser-melted fuse. A power source voltage Vpp necessary for the write operation is supplied from the external source.

[0125] Memory cells 304 each having a basic constitution illustrated in FIG. 1 are provided in 8 columns by 5 rows, and are selectively written one by one by the column decoder 300 and the row decoder 302. The read operation is performed in units of 8 memory cells 304 selected by the column by the mat selection signals MS0 to MS4. Read information is supplied to an address comparison circuit 305 as recovery address information CRA0 to CRA7 and is compared with the 8 bits corresponding to the access address signal at that time and the comparison results YSEN, YR are used for a redundancy selection control.

[0126] The gate oxide film of the transistor constituting the non-volatile memory element is formed by the same oxidization process as the gate oxide film used for the DRAM memory cell. Therefore, the non-volatile memory elements PM1, PM2 can be formed without adding any new process to the basic DRAM process. Here, the DRAM memory cell has a cross-sectional structure, for example, shown in FIG. 53.

Flash Memory

[0127] In FIG. 13, there is schematically illustrated the circuit block diagram of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention. A plurality of memory cells 310 illustrated in FIG. 8 are arranged in a matrix, and write date lines PDL1 to PDLn are connected to a write driver 311, read data lines RDL1 to RDLn are connected to a sense amplifier 312, write word lines PWL1 to PWLm and read word lines RWL1 to RWLn are connected to a word driver 313. When the write operation is performed, a column decoder 314 decodes a column address signal CADD to produce the selection signals of the write data lines PDL1 to PDLn and drives the selected write data line by the write driver 311. The selection of the write word lines PWL1 to PWLm when the write operation is performed is directed to the word driver 313 by a row decoder 316 for decoding a row address signal RADD. On the other hand, when the read operation is performed, a column decoder 315 decodes a column address signal CADD to produce the selection signal of the read data lines RDL1 to RDLn and amplifies the signal of the selected read data line by the sense amplifier 312 and produces it as read data DATA. The selection of the read word lines RWL1 to RWLm when the read operation is performed is directed to the word driver 313 by the row decoder 316 for decoding the row address signal RADD. The erase operation to the memory cells 310 is performed by one operation. Voltage to drive the word lines by the word driver 313 is switched by a word line driving voltage switching circuit 317. The voltage of the source line Vss is switched by a source line driving voltage switching circuit 318. The flash memory is controlled as a whole by a control circuit 319.

System LSI Recovery Fuse

[0128] In FIG. 14, there is schematically illustrated the plan view of a system LSI chip which is one example of a semiconductor integrated circuit in accordance with the present invention. The system LSI 320 illustrated in the drawing is provided with a large number of external connection electrodes 321 such as bonding pads or the like arranged at the peripheral portion of a semiconductor substrate and an external input/output circuit (3.3 VI/F) 322 and an analog input/output circuit (analog I/O) 323, both circuits being arranged inside the bonding pads, though not limited thereto. The external input/output circuit 322 and the analog input/output circuit 323 are operated by an external power source having a relatively high level like 3.3 volts. A level shifter 324 lowers the voltage of the external power source to a voltage of 1.8 volts for an internal power source. Inside the level shifter 324, there are provided a dynamic random access memory (DRAM) 325, a central processing unit (CPU) 326, a cache memory (CACH) 327, a logic circuit (LOG) 328, a phase-locked loop circuit (PLL) 329, an analog/digital conversion circuit (ADC) 330, a digital/analog conversion circuit (DAC) 331, and a built-in self test circuit (BIST) 332. What is designated by a reference numeral 333 is an electrically erasable writable non-volatile memory FUSE, for example, a flash memory. The DRAM 325, the CPU 326, the LOG 328, the CACH 327, and the BIST 332 are operated by the internal power source having a voltage of 1.8 V supplied by the level shifter 324. The DRAM 325, however, raises the internal power source voltage to form a word line selection level and uses it for the operational power source of the word driver and the like. In the data read operation, the flash memory (FUSE) 333 is operated by the internal power source voltage, but in the erase operation or in the write operation, it needs high voltage and the high voltage may be generated by an internal voltage boosting circuit or may be supplied by the external power source via a predetermined external connection electrode in a predetermined operational mode such as the EPROM write mode of the system LSI 320, which will be described later.

[0129] The above-mentioned flash memory (FUSE) 333 is used for storing the recovery information of the DRAM 325 (control information to replace a faulty memory cell with a redundant memory cell), and the flash memory (FUSE) 333 is used for storing the recovery information of the cache memory 327, and is provided, instead of a program circuit for recovery by fuse, though not limited thereto. The above flash memory 333 constitutes a programmable logic circuit in which its memory information determines the logic function of the output to the input. For example, the flash memory (FUSE) 333 functions as a logic circuit in which it performs a predetermined logic calculation to a plurality of bits of an address signal and holds the results of the calculation as data in advance and outputs a predetermined logic calculation result corresponding to a combination of logic values of the address input signal.

[0130] The above-mentioned system LSI 320 has a complementary MIS transistor (insulating gate field effect transistor) formed on one semiconductor substrate like a single crystal silicon by a single layer polysilicon gate process and the thickness of the gate oxide film of the MIS transistor is classified into two kinds, though not limited to this.

[0131] Each of the external input/output circuit 322, the analog input/output circuit 323, the DRAM 325, the flash memory 333, the ADC 330, and the DAC 331 has MIS transistors each having a gate length of 0.4 μm and a gate oxide film thickness of 8 nm in the case of using a 0.2 μm process technology, though not limited to this. This is because it is desirable for improving information holding performance of the flash memory that a tunnel oxide film composed of a gate oxide film is made comparatively thick and further because a certain level of withstand voltage (withstand voltage against the breakage of the gate oxide film) needs to be ensured against the operational voltage of the MIS transistor. Therefore, the gate insulating film of the MIS transistor constituting the non-volatile memory element of the above-mentioned flash memory and the gate insulating film of the MIS transistor included by the above-mentioned external interface circuit are made to have an equal film thickness in the range of permissible error due to variations in the process. Although the range of permissible error of the gate insulating film thickness due to variations in the process is about +0.5 nm for a target film thickness of 8.0 nm in a process for a minimum work size of 0.25 μm to 0.2 μm and about ±0.3 nm for a target film thickness of 6.5 nm in a process for a minimum work size of 0.18 μm to 0.15 μm, though it is not limited to this.

[0132] In contrast to this, the circuit operated by the internal power source voltage which is lowered to a comparatively lower level, that is, the logic circuit 328, the cache memory 327, or the CPU 326 is composed of a MIS transistor having a gate length of 0.2 μm and a gate film thick of 4 nm. The level shift circuit has the MIS transistor having both of the gate oxide film thicknesses, though it is not limited to this.

[0133] The gate electrodes of the MIS transistors different in the gate oxide film thickness from each other are composed of polysilicon layers having the same film thickness. Here, that the polysilicon layers have the same film thickness means that they are equal in film thickness to each other in the range of permissible error due to variations in the process. The range of permissible error due to variations in the process is about ±10% for a target film thickness of 30 nm to 200 nm, though it is not limited to this.

[0134] The above-mentioned gate oxide films which are to be equal in the film thickness to each other are formed by the same photo mask. Also, the above-mentioned polysilicon gates which are to be equal in the film thickness to each other are formed by the same photo mask. In this manner, by making the thickness of the gate oxide film of the non-volatile memory element having a single layer gate structure equal to that of the gate oxide film of the MIS transistor of the other circuit, it is possible to prevent the manufacturing process of the system LSI from being complicated and further to provide the non-volatile memory element of the flash memory with a performance of holding information for a considerably long time.

[0135] In FIG. 15, there is shown the testing flow chart of a system LSI in accordance with the present invention. After a wafer is completed (S1), first, a logic circuit test is conducted by using a logic tester (S2) and then a memory test is done on the chip passing the test (S3). The memory test is conducted by the self-diagnostics of the built-in self test (BIST) circuit 332 mounted on the chip and the obtained fault information is memorized as the write data in the above-mentioned flash memory (FUSE) 333 to constitute a programmable logic circuit determined by the memorized information to complete a fault recovery. Next, a chip whose faulty memories have been recovered is fabricated in a predetermined package (S4) and is subjected to an operation test in which temperature and power voltage are accelerated (burn-in test) (S5). If there happens faulty refresh, for example, in the memory cell of the DRAM 325 in this burn-in test, a second recovery of replacing a faulty bit with a redundant bit is conducted and recovery information is written into the flash memory (FUSE) 333. Then, a grading test is conducted on the logic circuit (S6) to grade it by an operating speed and the like. Then, the system LSI is shipped.

DRAM Hybrid Recovery Fuse

[0136] In FIG. 16, there is schematically illustrated the chip plan view of a 1-G bit DRAM 340 which is one example of a semiconductor integrated circuit in accordance with the present invention. This DRAM 340 is composed of 4 banks of memory arrays 341 to 344 and has bonding pads 345 arranged in the center. A Y-decoder and a main amplifier are mounted on each memory array, as shown by reference numerals 351 to 354. A word driver 355A, an X-decoder 356A, a word driver 357A are shared by the memory arrays 341, 342, and a word driver 355B, an X-decoder 356B, and a word driver 357B are shared by the memory arrays 343, 344.

[0137] The recovery fuses including two sets of 2000 laser fuses designated by reference numerals 346, 347 and an electric fuse composed of a flash memory with 100 bits designated by a reference numeral 348 are arranged in the center. Describing the relationship between the laser fuses 346, 347 and the electric fuse 348 in a circuit connection, for example, it is the relationship between a Flash fuse and a laser-melted in FIG. 52.

[0138] In FIG. 17, there is shown a testing flow chart of the above DRAM 340. After a wafer is completed (S1), first, a memory test is done on a chip by using a memory tester (S2). To replace a detected faulty bit with a redundant bit or a redundant mat, a laser fuse recovery is conducted (S3). Next, the DRAM 340 is fabricated in a predetermined package (S4) and is subjected to a burn-in test of an operation test, in which temperature and power voltage are accelerated (S5), and a grading test (S6). If a fault such as faulty refresh happens in the memory cell of the DRAM 340 in this burn-in test (S5), recovery information is written into the electric fuse 348 made of a flash memory, as a second recovery by the electric fuse, whereby a faulty bit is replaced by a redundant bit. Then, after this electric fuse recovery, a memory test is conducted on the recovered address (S7). Then, the system LSI is shipped.

Flash Memory

[0139] In FIG. 18 to FIG. 21, the cross-sectional structural views of a flash memory which is one example of a semiconductor integrated circuit in accordance with the present invention are illustrated for each manufacturing process.

[0140] To begin with, as shown in FIG. 18, a trench type element isolating region 24 having a depth of 300 nm is formed on a p-type semiconductor substrate 21, and there are formed an n-type semiconductor region 22 which is to be a control gate of a flash memory (flash section) and on which a p-type channel MIS transistor (PMOS-Tr) is to be formed and a p-type semiconductor region 23 on which an n-type channel MIS transistor (NMOS-Tr) is to be formed, a gate oxide film 26 having a thickness of 7 nm is grown, and then an n-type impurity layer 25 for adjusting an initial threshold voltage is introduced only into the read MIS transistor section of the flash memory.

[0141] Next, as shown in FIG. 19, a polysilicon film 27 is deposited which has a thickness of 200 nm and is to be the gate electrode of a peripheral circuit transistor and the floating gate of the flash memory, and a side spacer 30 formed of silicon nitride film having a thickness of 80 nm is formed. Then, the surface region of the n-type semiconductor region 22 which is to be the control gate of the flash memory cell, an n-type diffusion layer 31 which is to be the source and drain regions of the n-type channel MIS transistor NMOS-Tr, and a p-type diffusion layer 32 which is to be the source and drain regions of the p-type channel MIS transistor PMOS-Tr are formed, and a cobalt silicide film 29 having a thickness of 20 nm is formed selectively on the surface region of the above-mentioned polysilicon film 27, the surface region of the n-type diffusion layer 31, and the p-type diffusion layer 32.

[0142] Further, as shown in FIG. 20, a first interlayer insulating film 33 is deposited, a contact hole is made, a first metal wiring layer 34 is deposited, and a predetermined pattern is formed thereon. Further, a second interlayer insulating film 35 is deposited, a first through hole is made, a second metal wiring layer 36 is deposited, and a pattern is formed thereon.

[0143] Finally, as shown in FIG. 21, a third interlayer insulating film 37 is deposited, a second through hole is made, a third metal wiring layer 38 is deposited, and a pattern is formed thereon. Then, a final passivation film is deposited and an opening is made in a bonding pad. This is the end of the manufacturing process of the flash memory.

Cell Structure with High Reliability

[0144] In FIG. 22, there is illustrated an equivalent circuit diagram of a flash memory cell with high reliability which is another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. In the memory cell shown in the drawing, the respective floating gates of three non-volatile memory elements PM1, PM2, PM3 which are connected in parallel to each other are arranged as the gate electrodes of read MIS transistors DM1, DM2, DM3. The three read MIS transistors DM1, DM2, DM3 are connected in series to each other to establish an OR logic. By selecting a write data line PDL and a write word line PWL, the write operation is performed to the three non-volatile memory cells PM1, PM2, PM3 at the same time to hold electrons in all the floating gates, and the three read MIS transistors DM1, DM2, DM3 are cut off at the same time. In the case where charges happen to be caused to leak, in the state where charges are held, by the faults of the gate oxide film and the moisture introduced from the outside, even if the above-mentioned faults are encountered in two elements out of the three non-volatile memory cells PM1, PM2, PM3, the memory cell does not become faulty because a read current path is held cut off. This constitution can further improve a performance of holding data for a long time and realize a remarkable reduction in the rate of faulty reading.

Small Cell Structure

[0145] In FIG. 23, there is illustrated an equivalent circuit diagram of a small area flash memory cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. In the memory cell shown in the drawing, the floating gate of a non-volatile memory cell PM is arranged as the gate electrode of a read MIS transistor DM and hence a cell area can be reduced to a minimum. This is a measure against the charge gain. Further, in order to ensure charge holding characteristics, in other words, to increase resistance to data retention, the gate oxide film to be used is formed in a thickness of 10 nm or more.

Voltage Sense Type Cell

[0146] In FIG. 24, there is illustrated an equivalent circuit diagram of a voltage sense type flash memory cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. In the memory cell shown in the drawing, the respective floating gates of two non-volatile memory elements PM1, PM2 connected in parallel to each other are arranged as the gate electrodes of read MIS transistors DM1, DM2 connected in series to each other and a read MIS transistor DM1 is arranged in series between the read MIS transistors DM1 and a power source line Vcc. A read operation is performed by selecting a read word line RWL and by sensing voltage produced on a read data line RDL. That is, a change in the electric potential of the read data line RDL is detected by a voltage detection type sense amplifier (not shown) or the like according to whether the read MIS transistors DM1, DM2 are in the cut-off state of not.

Metal Cover Type Memory Cell

[0147] In FIG. 25, there is illustrated a plane layout of a metal cover type flash memory cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. Also, in FIG. 26, there is illustrated the cross sectional view taken on a line C-C′ in FIG. 25. In the memory cell shown in the drawing, a third metal wiring layer 41 constituting a read data line RDL is arranged such that it covers floating gate regions 7, 27 arranged below to prevent the held charges from being excited and emitted from the floating gates by the injection of x-rays, radioactive rays, light or the like to further improve a performance of holding data for a long time.

[0148] In FIG. 27, there is illustrated a plane layout of a metal cover type flash memory cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. Also, in FIG. 28, there is illustrated the cross sectional view taken on a line D-D′ in FIG. 27. In the memory cell shown in the drawing, a second metal wiring layer 42 constituting a write data line PDL is arranged such that it covers floating gate regions 7, 27 arranged below to prevent the held charges from being excited and emitted from the floating gates by the injection of x-rays, radioactive rays, light or the like to further improve a performance of holding data for a long time.

PMOS Cell

[0149] In FIG. 29, there is illustrated an equivalent circuit diagram of a flash memory cell using a p-channel type MIS transistor which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. In the memory cell shown in the drawing, read MIS transistors EM1, EM2 are p-channel type MIS transistors and the read MIS transistors EM1, EM2 are connected in parallel to each other so as to constitute an OR logic. In the voltage-current characteristics shown in FIG. 30, the initial threshold voltage (Vthpem) of the read MIS transistors EM1, EM2 are normally off in the initial state and become on when electrons are held in the floating gate. Therefore, even if the charges in one of the floating gates leak in the state where charges are held to produce faulty conditions, the memory cell does not produce faulty reading because a read current path is held at the ON state. Therefore, this can improve a performance of holding data for a long time and realize a reduction in the rate of faulty reading. In FIG. 31, there is illustrated a plane layout of the memory cell in FIG. 29.

2 NAND Type Cell

[0150] In FIG. 32, there is illustrated an equivalent circuit diagram of a 2 NAND type flash memory cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. The memory cell shown in the drawing has a so-called 2 NAND logic whose read circuit section is constituted by two p-channel type MIS transistors EM1, EM2, which are connected in parallel to each other, and two n-channel type MIS transistors DM1, DM2 which are connected in series to each other. Since a read data line is connected to the junction of the p-channel type MIS transistors EM1, EM2 and the n-channel type MIS transistors DM1, DM2, that is, the output of 2 NAND, it can produce approximately a power source voltage amplitude as a data line voltage when a read operation is performed, which eliminates the need for a sense amplifier. The initial threshold voltages of the p-channel type MIS transistors EM1, EM2 and the n-channel type MIS transistors DM1, DM2 are set in such a way that they are symmetrically on or off according to whether charges are injected into or ejected from the floating gate, as is clear from the voltage-current characteristics shown in FIG. 33. As is clear from FIG. 34 showing the plane layout of the memory cell in FIG. 32, this memory cell has a large cell area because it has many constituent elements but has an advantage of eliminating the need for a sense amplifier and does not always increase a memory cell module area.

Self-Learning Type 2 NAND Gate

[0151] In FIG. 35, there is illustrated a circuit diagram of a self-learning type 2 NAND gate which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. The 2 NAND gate shown in the drawing has two p-channel type MIS transistors LPM1, LPM2 connected in parallel to each other between a power source line Vcc and an output OUT and two n-channel type MOS transistors LNM1, LNM2 connected in series to each other between the non-volatile memory element PM2 and the p-channel type MIS transistor LPM1. The gates of the MIS transistors LPM2, LNM2 are common to the floating gate of the non-volatile memory element PM2 and the gates of the MIS transistors LPM1, LNM1 are common to the floating gate of the non-volatile memory element PM1. The non-volatile memory elements PM1, PM2 are arranged in parallel between a source line Vss and a drain line Vpp. To the source line Vss is applied the ground electric potential of the circuit and to the drain line Vpp is applied a high voltage for writing.

[0152] The 2 NAND gate shown in the drawing can provide a NAND output OUT according to the input signals IN1, IN2. Further, since the source line of the non-volatile memory elements PM1, PM2 is connected to the ground voltage of the circuit and the drain line thereof is connected to the high voltage for writing, the 2 NAND gate has a self-learning function in which signal transmission characteristic is shifted to the high level output side, as shown in FIG. 36, in proportion to the number of inputs of the high level pulse signals or the number of high level pulses of the input signals IN1, IN2. Here, in FIG. 37, there is illustrated the plane layout of the memory cell in FIG. 35.

Gate Oxide Film Degradation Monitor

[0153] In FIG. 38, there is illustrated the circuit diagram of a gate oxide film degradation monitor to which a non-volatile memory element in accordance with the present invention is applied. A read MIS transistor DM1 and a select MIS transistor SM1 are connected in series to a non-volatile memory element P1 and, similarly, a read MIS transistor DM2 and a select MIS transistor SM2 are connected in series to a non-volatile memory element P2. Each of the non-volatile memory elements P1, P2 is composed of a standard MIS transistor and a capacitor MIS transistor. The drain voltages of the read MIS transistors DM1, DM2 are made the differential inputs to a differential amplifier 370. On the other hand, the control gate of the non-volatile memory element P2 is connected to the ground voltage Vss of the circuit. The control gate of the other non-volatile memory element P1 and the gate electrodes of the select MIS transistors SM1, SM2 are connected to the output of a complementary inverter circuit receiving a signal MG. The divided voltages of the DM1, DM2 vary in the practical use according to the degradation in characteristics caused by the hot electrons (HE) injected into the floating gates of the non-volatile memory element. The voltage differential between the DM1, DM2 is amplified by the differential amplifier circuit 370, which makes it possible to monitor the amount of hot electrons (HE) injected into the floating gates.

Differential Amplifier Type Cell

[0154] In FIG. 39, there is illustrated an equivalent circuit diagram of a differential amplifier type flash cell which is still another example of a non-volatile information memory cell included by a semiconductor integrated circuit in accordance with the present invention. The information memory cell shown in the drawing is constituted in such a way that the cell structures shown in FIG. 23 are provided on the inversion side and on the non-inversion side, respectively, and both of them are writable separately. That is, the information memory cell has a series circuit composed of a non-volatile memory element PM1, a read MIS transistor DM1 and a select MIS transistor SM1, and a series circuit composed of a non-volatile memory element PM2, a read MIS transistor DM2 and a select MIS transistor SM2, wherein the drain of the read MIS transistor DM1 is connected to one complementary read data line RDLT and the drain of the read MIS transistor DM2 is connected to the other complementary read data line RDLB and a write word line PWLT is connected to the control gate of the non-volatile memory element PM1 and a write word line PWLB is connected to the control gate of the non-volatile memory element PM2. One of the non-volatile memory elements PM1, PM2 is brought into a writing state and the other is brought into an erasing state to memorize information. Here, in FIG. 40, there is illustrated the plane layout of the flash cell shown in FIG. 39.

Fuse Module with Built-in ECC

[0155] In FIG. 41, there is illustrated the block diagram of a fuse module which is still another example of a semiconductor integrated circuit in accordance with the present invention. The fuse module shown in the drawing has: a non-volatile memory 380 including five non-volatile memory blocks (7 b File#0-7 b File#4) as a non-volatile information memory cell group; a Hamming code generator 381 for generating a Hamming code to the 35-bit data q0-34 outputted by the non-volatile memory 380; a non-volatile memory 382 including a non-volatile memory block (7 b File#5) for memorizing the Hamming code generated by the Hamming code generator 381; an error correction circuit 383 which can receive the Hamming code outputted by the non-volatile memory block 382 and the 35-bit data q0-34 outputted by the non-volatile memory 380 and make an error correction to the received data; and a control circuit 384. Write data into the non-volatile memory 380 is given as d0-6 from the outside. The output of the error correction circuit 383 is shown as qc 0-34. To the control circuit 384 are applied an address signal a0-2 for selecting the non-volatile memory blocks 7 b File#0 7 b File#4, a direction signal rd for the read operation, and a direction signal prg for the write operation.

[0156] In FIG. 48, there is illustrated one example of a logic for generating a Hamming code by the above-mentioned Hamming code generator 381 and one example of an error detection and correction logic by the above-mentioned error correction circuit 383.

[0157] In FIG. 42, there is illustrated an example of non-volatile memory blocks 7 b File#0-7 b File#5. Each of the non-volatile memory blocks has 7 bits of unit information cells 386 which are constituted equally to each other. The unit information cells 386 are controlled by a bias controller 385. The bias controller 385 produces control signals rd, prg, set, s1, and cg to the unit information cells 386 based on the direction from the control circuit 384.

[0158] In FIG. 44, there is illustrated one example of the unit information cell 386. The unit information cell 386 is composed of a memory cell section 387 and a write/read control circuit 388.

[0159] The memory cell 387 includes a non-volatile memory element PM1 which is composed of a MIS capacitor element PM1 b and a MIS transistor PM1 a and a non-volatile memory element PM2 which is composed of a MIS capacitor element PM2 b and a MIS transistor PM2 a, as is the case shown in FIG. 54.

[0160] In the constitution in FIG. 44, read MIS transistors DM1, DM2 are composed of enhancement type transistors. The voltage-current characteristics of the MIS transistors DM1, DM2 are shown in FIG. 51. The voltage-current characteristics to a control gate voltage cg are different between the writing state and the erasing state of the non-volatile memory cell corresponding thereto. A reference numeral “1” designates the writing state and “0” designates the erasing state.

[0161] The drain of the read MIS transistor DM2 is connected to a control node pu via n-channel type MIS transistors TR3, TR4 and the electric potential of a junction node of the transistors TR3 and TR4 is applied to a write/read control circuit 388 as an output r1. The above-mentioned MIS transistors PM1 a, PM2 a are connected to a control node w1 via n-channel type MIS transistors TR1, TR2. The gate electrodes of the transistors TR1 to TR4 are biased by a power source voltage. A reference character cg corresponds to a control gate and s1 corresponds to a source line.

[0162] In FIG. 46, there is illustrated the layout pattern of the memory cell section 387. In FIG. 46, the memory cell section 387 is formed in a p-type well region PW and in an n-type well region NW. A reference character N+ designates an n-type diffusion region, which is formed in the p-type well region PW and is made the source electrode and the drain electrode of the n-channel MIS transistor, and a reference character AG designates the gate electrodes of the TR1, TR2, and a reference character CONT designates a contact hole, and P+ designates a diffusion layer which is formed in the n-type well region NW and is made the control gate constituted by the PM1 b, PM2 b.

[0163] In FIG. 43, there is shown the control states of the unit information cells 386 by the above-mentioned bias controller 385. In FIG. 47, there is illustrated one example of a timing chart of a program operation to the unit information cell 386 according to the control state. In FIG. 45, there is shown a read timing chart in the state where a fuse module is practically used after the program is completed to the unit information cell 386.

[0164] Operations illustrated in these drawings will be summarized. In the write operation, terminals s1, cg are disposed at 5V and a terminal w1 is disposed at 0V to turn on the non-volatile memory cells PM1, PM2 to inject hot electrons into the floating gate from the terminal s1 side. In the erase operation, only the terminal s1 is disposed at 5V to emit electrons from the floating gate by the tunnel emission. In the read operation, the terminal pu is disposed at 1.5V and the terminal cg is disposed at 1.5V to latch the electric potential of the terminal r1 determined by the switching state or the mutual conductance state of the transistors DM1, DM2 according to the accumulated charges on the floating gate into a latch circuit at a later position. In the read operation, both of the source electrode (s1) and the drain electrode (w1) of the non-volatile memory elements PM1 a, PM2 a are disposed at 0V. Therefore, in the read operation, no weak hot electron is injected into the floating gate from the transistors PM1 a, PM2 a. At this time, although weak hot electrons are going to be injected into the floating gate from the read MIS transistors DM1, DM2, since the TR4, TR3, DM2, DM1 are vertically stacked, the drain voltages of the read MIS transistors DM1, DM2 become smaller than pu and the control level of cg in the read operation is also low, so it can be concluded the injection of the hot electrons is substantially negligibly small. Accordingly, the rate of faulty reading of the non-volatile memory elements PM1, PM2 themselves is reduced.

[0165] Further, as described above, since the Hamming code generator 381, the non-volatile memory 382, and the error correction circuit 383 realize an ECC circuit, granting that the data read from the non-volatile memory blocks 7 bFile#D to 7 bFile#4 of the non-volatile memory 389 is faulty, they are automatically corrected and hence the rate of faulty reading can be reduced ultimately. In order to assure such an error correcting function by the ECC circuit, in the above-mentioned non-volatile memories 380, 382, a program circuit for writing into the non-volatile memory blocks 7 bFile#0 to 7 bFile#4, 7 bFile#5 has an operation mode of prohibiting writing into the non-volatile memory blocks 7 bFile#0 to 7 bFile#4, 7 bFile#5 when the ECC circuit is effectively operated. For example, although not shown, a 1-bit non-volatile flag for indicating whether the write operation is completed or is not yet completed is provided on the non-volatile memory 380, and when the non-volatile flag is set by the controller 384, the above-mentioned operation mode of prohibiting writing is directed to the above-mentioned program circuit.

[0166] Up to this point, while the invention made by the present inventor has been described specifically based on the preferred embodiments, it is not intended to limit the present invention to the preferred embodiments, but it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

[0167] For example, the above-mentioned non-volatile memory element can be applied widely to a non-volatile memory element and the like for constituting a programmable logic in addition to the one for storing recovery information in a recovery circuit.

[0168] Effects produced by the typical invention disclosed in the present application will be described briefly in the following.

[0169] That is, it is possible to improve a long-term information holding performance by means of a memory cell using a non-volatile memory element. It is possible to remarkably reduce the rate of faulty reading without adding an absolutely new process to an ordinary logic circuit process or a general-purpose DRAM process. It is possible to provide a technology for utilizing a flash memory cell composed of a single layer polysilicon gate as a memory module formed in a semiconductor device or the recovery circuit of a memory circuit.

[0170] It is possible to provide a semiconductor integrated circuit like a system LSI mounted with a non-volatile memory having an excellent data holding performance described above, a DRAM and the like, by employing a single gate process like a single layer polysilicon gate process. Further, it is easy to apply the non-volatile memory element to an LSI in which a non-volatile memory and a logic LSI, or a non-volatile memory and a DRAM are mounted on the same semiconductor substrate because a highly reliable non-volatile memory can be formed without adding any process to a conventional standard CMOS manufacturing process. Therefore, it is possible to provide a system LSI mounted with flash memories without increasing a manufacturing cost. 

What is claimed is:
 1. A semiconductor device comprising: a non-volatile memory element including a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode, and capable of having different threshold voltages; a read transistor element including a second source electrode, a second drain electrode and the floating gate electrode as a gate electrode, and capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element; and transmission means of a signal generated according to the mutual conductance of the read transistor element.
 2. A semiconductor device according to claim 1, wherein the ground voltage of a circuit is applied to the first source electrode and the first drain electrode in a read operation.
 3. A semiconductor device according to claim 1 or claim 2, wherein the read transistor element is a depression type MIS transistor and the control gate electrode is set at a non-select level in a read operation.
 4. A semiconductor device according to any one of claims 1 to 3, wherein the read transistor element is an enhancement type MIS transistor and the control gate electrode is set at a select level in a read operation.
 5. A semiconductor device according to claim 1, wherein the non-volatile memory element includes a MIS capacitor element having a capacitor electrode on a first semiconductor region functioning as a control gate electrode via an insulating layer and a MIS transistor including a first source electrode, a first drain electrode and a gate electrode which are formed on a second semiconductor region, the capacitor electrode being connected to the gate electrode and functioning as a floating gate electrode.
 6. A semiconductor device according to claim 1, wherein the non-volatile memory element includes; a first conductivity type first well region formed on a semiconductor substrate; a second conductivity type second well region formed on the semiconductor substrate; a second conductivity type first source electrode region which is formed on the first well region and is to be connected to a first signal line; a second conductivity type first drain electrode region which is formed on the first well region and is to be connected to a second signal line; a first insulating film formed on the principal surface of the first well region at the position between the first source electrode region and the first drain electrode region; a second insulating film formed on the principal surface of the second well region; a floating gate electrode region formed on the first and second insulating films; and a control gate electrode region which is formed on the second well region and is to be connected to a third signal line.
 7. A semiconductor device according to claim 1, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and wherein the pair of read transistor elements are connected in parallel to the transmission means.
 8. A semiconductor device according to claim 1, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and wherein the pair of read transistor elements are connected in series to the transmission means.
 9. A semiconductor device according to claim 8, further comprising a plurality of unit information cells, each of which is composed of the pair of non-volatile memory elements and the pair of read transistor elements, and an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, wherein the plurality of unit information cells are made the memory circuit of recovery information to a circuit to be recovered.
 10. A semiconductor device according to claim 9, further comprising a fuse program circuit for memorizing recovery information according to the melting state of a fuse element as another recovery information memory circuit to the circuit to be recovered.
 11. A semiconductor device according to claim 9, wherein the circuit to be recovered is the memory cell array in which a DRAM is built.
 12. A semiconductor device according to claim 9, wherein the circuit to be recovered is the memory cell array of a DRAM in which a microcomputer is built.
 13. A semiconductor device according to claim 9, wherein the circuit to be recovered is the memory cell array of an SRAM in which a microcomputer is built.
 14. A semiconductor device according to claim 13, wherein the electric program circuit has an operation mode of prohibiting writing into the unit information cell, when an ECC circuit is effective.
 15. A semiconductor device according to claim 8, further comprising a plurality of unit information cells each of which is composed of the pair of non-volatile memory cells and the pair of read transistor elements, wherein a part of the plurality of unit information cells are made a region for holding an error correction code to the memory information of the remaining unit information cells, an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, and an ECC circuit capable of making an error correction to the read information of the plurality of unit information cells.
 16. A semiconductor device comprising: a non-volatile memory element including a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode, and capable of having different threshold voltages; a read transistor element including a second source electrode, a second drain electrode and the floating gate electrode as a gate electrode, and capable of having different switching states according to the threshold voltage of the non-volatile memory element; and transmission circuit of a signal generated according to the switching state of the read transistor element.
 17. A semiconductor device according to claim 16, wherein the ground voltage of a circuit is applied to the first source electrode and the first drain electrode in a read operation.
 18. A semiconductor device according to claim 16, wherein the read transistor element is a depression type MIS transistor and the control gate electrode is set at a non-select level in a read operation.
 19. A semiconductor device according to claim 16, wherein the read transistor element is an enhancement type MIS transistor and the control gate electrode is set at a select level in a read operation.
 20. A semiconductor device according to claim 16, wherein the non-volatile memory element includes a MIS capacitor element having a capacitor electrode formed on a first semiconductor region functioning as a control gate electrode via an insulating layer and a MIS transistor including a first source electrode, a first drain electrode and a gate electrode which are formed on a second semiconductor region, the capacitor electrode being connected to the gate electrode and functioning as a floating gate electrode.
 21. A semiconductor device according to claim 16, wherein the non-volatile memory element includes; a first conductivity type first well region formed on a semiconductor substrate; a second conductivity type second well region formed on the semiconductor substrate; a second conductivity type first source electrode region which is formed on the first well region and is to be connected to a first signal line; a second conductivity type first drain electrode region which is formed on the first well region and is to be connected to a second signal line; a first insulating film formed on the principal surface of the first well region at the position between the first source electrode region and the first drain electrode region; a second insulating film formed on the principal surface of the second well region; a floating gate electrode region formed on the first and second insulating films; and a control gate electrode region which is formed on the second well region and is to be connected to a third signal line.
 22. A semiconductor device according to claim 16, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and wherein the pair of read transistor elements are connected in parallel to the transmission means.
 23. A semiconductor device claim 16, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element , and wherein the pair of read transistor elements are connected in series to the transmission means.
 24. A semiconductor device according to claim 23, further comprising a plurality of unit information cells, each of which is composed of the pair of non-volatile memory elements and the pair of read transistor elements, and an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, wherein the plurality of unit information cells are made the memory circuit of recovery information to a circuit to be recovered.
 25. A semiconductor device according to claim 23, further comprising a fuse program circuit for memorizing recovery information according to the melting state of a fuse element as another recovery information memory circuit to the circuit to be recovered.
 26. A semiconductor device according to claim 23, wherein the circuit to be recovered is the memory cell array in which a DRAM is built.
 27. A semiconductor device according to claim 23, wherein the circuit to be recovered is the memory cell array of a DRAM in which a microcomputer is built.
 28. A semiconductor device according to claim 23, wherein the circuit to be recovered is the memory cell array of an SRAM in which a microcomputer is built.
 29. A semiconductor device according to claim 28, wherein the electric program circuit has an operation mode of prohibiting writing into the unit information cell, when an ECC circuit is effective.
 30. A semiconductor device according to claim 16, further comprising a plurality of unit information cells each of which is composed of the pair of non-volatile memory cells and the pair of read transistor elements, wherein a part of the plurality of unit information cells are made a region for holding an error correction code to the memory information of the remaining unit information cells, an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, and an ECC circuit capable of making an error correction to the read information of the plurality of unit information cells.
 31. A semiconductor device comprising: a non-volatile memory element including a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode, and capable of having different threshold voltages; a read transistor element including a second source electrode, a second drain electrode and the floating gate electrode as a gate electrode, and capable of having different threshold voltages according to the threshold voltage of the non-volatile memory element; and transmission circuit of a signal generated according to the threshold voltage of the read transistor element.
 32. A semiconductor device according to claim 31, wherein the ground voltage of a circuit is applied to the first source electrode and the first drain electrode in a read operation.
 33. A semiconductor device according to claim 31, wherein the read transistor element is a depression type MIS transistor and the control gate electrode is set at a non-select level in a read operation.
 34. A semiconductor device according to claim 31, wherein the read transistor element is an enhancement type MIS transistor and the control gate electrode is set at a select level in a read operation.
 35. A semiconductor device according to claim 31, wherein the non-volatile memory element includes a MIS capacitor element having a capacitor electrode on a first semiconductor region functioning as a control gate electrode via an insulating layer and a MIS transistor including a first source electrode, a first drain electrode and a gate electrode which are formed on a second semiconductor region, the capacitor electrode being connected to the gate electrode and functioning as a floating gate electrode.
 36. A semiconductor device according to claim 31, wherein the non-volatile memory element includes; a first conductivity type first well region formed on a semiconductor substrate; a second conductivity type second well region formed on the semiconductor substrate; a second conductivity type first source electrode region which is formed on the first well region and is to be connected to a first signal line; a second conductivity type first drain electrode region which is formed on the first well region and is to be connected to a second signal line; a first insulating film formed on the principal surface of the first well region at the position between the first source electrode region and the first drain electrode region; a second insulating film formed on the principal surface of the second well region; a floating gate electrode region formed on the first and second insulating films; and a control gate electrode region which is formed on the second well region and is to be connected to a third signal line.
 37. A semiconductor device according to claim 31, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and wherein the pair of read transistor elements are connected in parallel to the transmission means.
 38. A semiconductor device according to claim 31, wherein the non-volatile memory element is provided in a pair and the read transistor element is provided in a pair, wherein the floating gate electrode of one of the non-volatile memory elements is shared by one of the read transistor elements and the floating gate electrode of the other non-volatile memory element is shared by the other read transistor element, and wherein the pair of read transistor elements are connected in series to the transmission means.
 39. A semiconductor device according to claim 38, further comprising a plurality of unit information cells, each of which is composed of the pair of non-volatile memory elements and the pair of read transistor elements, and an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, wherein the plurality of unit information cells are made the memory circuit of recovery information to a circuit to be recovered.
 40. A semiconductor device according to claim 38, further comprising a fuse program circuit for memorizing recovery information according to the melting state of a fuse element as another recovery information memory circuit to the circuit to be recovered.
 41. A semiconductor device according to claim 38, wherein the circuit to be recovered is the memory cell array in which a DRAM is built.
 42. A semiconductor device according to claim 38, wherein the circuit to be recovered is the memory cell array of a DRAM in which a microcomputer is built.
 43. A semiconductor device according to claim 38, wherein the circuit to be recovered is the memory cell array of an SRAM in which a microcomputer is built.
 44. A semiconductor device according to claim 43, wherein the electric program circuit has an operation mode of prohibiting writing into the unit information cell, when an ECC circuit is effective.
 45. A semiconductor device according to claim 31, further comprising a plurality of unit information cells each of which is composed of the pair of non-volatile memory cells and the pair of read transistor elements, wherein a part of the plurality of unit information cells are made a region for holding an error correction code to the memory information of the remaining unit information cells, an electric program circuit to the non-volatile memory elements of the plurality of unit information cells, and an ECC circuit capable of making an error correction to the read information of the plurality of unit information cells. 